The present invention relates in general to semiconductor die, and more particularly to testing of semiconductor die using wells.
Semiconductor manufacturers have the cost saving goal of detecting and screening out defective integrated circuits as early as possible in the manufacturing process. In addition, the requirement of supplying xe2x80x9cknown good diexe2x80x9d to multi-chip module (MCM) manufacturers has increased the importance of this goal.
During a typical semiconductor manufacturing process, a plurality of integrated circuits are formed as individual die on a semiconductor wafer. At present, each semiconductor wafer generally has dozens to hundreds of individual die formed thereon. As integration geometries decrease and the size of semiconductor wafers increase, the number of integrated circuit die formed on each wafer will most likely increase.
While the die are still in wafer form, each die is probed in order to determine whether each die passes a very basic opens/shorts test (e.g. a test for electrical opens or electrical shorts). In some cases, a full functional test is also performed using the probe equipment. However, no reliability testing is performed because it would be too costly to tie up the probe equipment testing one or a few die at a time for the hours required for reliability testing.
The purpose of the wafer level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less money that is wasted on further processing of defective die.
The die are then separated or singulated into individual die using any one of a variety of singulation techniques. In most cases, each die is then packaged in an integrated circuit package. Once the die have been packaged, thorough electrical testing is performed on each of the packaged integrated circuits. The purpose of the thorough electrical testing is to determine whether each packaged integrated circuit properly performs the functionality specified by the semiconductor manufacturer. The tested, packaged integrated circuits are then sold.
In some cases, the packaged integrated circuits also undergo a reliability testing procedure called burn-in. Burn-in testing involves the testing of an integrated circuit for an extended period of time while the temperature of the integrated circuit is elevated above room temperature. In some cases, the heat generated by the integrated circuit itself is sufficient to elevate the temperature of the integrated circuit. In other cases, the temperature of the integrated circuit is raised by an apparatus external to the integrated circuit (e.g. a burn-in oven in which the packaged integrated circuits are placed).
Alternately, instead of or in addition to burn-in testing, cold temperature reliability testing may be performed. Cold temperature reliability testing involves the testing of an integrated circuit for an extended period of time while the temperature of the integrated circuit is decreased below room temperature.
Semiconductor manufacturers spend a significant amount of money packaging defective die which pass the testing performed during probing, but which do not pass the reliability testing after packaging. In addition, the probe testing is redundant in that the same electrical tests are again performed on the individual integrated circuits after packaging.
The cost saving goal of detecting and screening out defective die as early as possible in the manufacturing process is especially important in the context of multi-chip modules (MCMs). Multi-chip modules (MCMs) are electronic modules that include a plurality of integrated circuit die which are packaged together as one unit. Multi-chip modules are becoming more widely used.
For multi-chip modules, it is quite costly to replace one or more failed die once the die have been bonded onto a substrate. Therefore, it is desirable to determine whether or not a die is fully functional and is reliable before the die is packaged as part of a multi-chip module. In addition, many manufacturers of multi-chip modules are requiring that semiconductor manufacturers sell them fully tested xe2x80x9cknown good diexe2x80x9d which have passed reliability tests and which are not packaged in an integrated circuit package.
As summarized above, testing of xe2x80x9cknown good diexe2x80x9d has become particularly important in modem semiconductor manufacturing. In this regard, various testing procedures have been devised with respect to semiconductor die that have bond pads to which are connected wire bonds, known in the art as a wirebond die. One example of a portion of an apparatus to test and burn-in such wirebond die is shown in FIG. 1.
FIG. 1 illustrates a prior art structure including carrier 10 which is connected to socket 12, which in turn is connected to testing equipment (not shown) for testing and burn-in of die 50. As shown, carrier 10 includes a forced delivery mechanism 14 which is connected to lid 16 through a biasing member (e.g. a spring). The force delivery mechanism is placed to overlie die 50 and bias die 50 in a downward direction such that the wirebond pads around the outer periphery of the die are biased against carrier contacts 18. As shown, the carrier contacts 18 have a xe2x80x9cmushroomxe2x80x9d shape, and are connected to interconnects 20 which extend over compliant material. The interconnects 20 are in turn connected to electrical contacts (not shown) extending through the socket 12.
While the apparatus shown in FIG. 1 including carrier 10 and socket 12 may be used to test and burn-in wirebond-type die, it is not particularly adapted for testing and burn-in of xe2x80x9cbumpedxe2x80x9d semiconductor die, such as die having bumps formed on an active surface thereof by the known Control Collapsed Chip Connection technology (xe2x80x9cC4xe2x80x9d). As is known in the art, such bumped die have a relatively large array of solder bumps provided on the active surface of the semiconductor die. The bumped die is configured to be inverted and placed on a plastic or ceramic substrate, and the solder bumps are reflowed to effect mechanical and electrical connection between the bumped die and the substrate. However, the bumps formed on the die are at a relatively fine pitch, and are formed in a relatively large number. For example, a common C4 bump is on the order of 125 microns in diameter and adjacent bumps are spaced apart from each other by 125 micron spaces.
Accordingly, the array is formed at a relatively fine pitch, typically on the order of 250 microns. In current applications, a typical microprocessor semiconductor die can have on the order of one thousand or greater C4 bumps.
Because of the relatively large number, high density and fine feature size associated with bumped die, numerous difficulties exist with testing and burn-in. More particularly, in an attempt to test or burn-in a bumped die, the present inventors attempted to modify the known carrier 10 depicted in FIG. 1 for use with a C4 bumped die, which brought to light several problems. First, as shown in FIG. 1, the carrier contact 18 has somewhat of a xe2x80x9cmushroomxe2x80x9d shape, wherein the upper contact surface of the carrier contact 18 is roughened to have a texture which contacts the C4 bumps. This texture is effective to break a native oxide on wirebond pads, to make ohmic contact to the wirebond pads. However, this same texture has the effect of roughening and pitting the C4 bumps on the die. As a result of the pitting, it was found that the vision equipment utilized for alignment during the first level packaging operation (i.e., bonding of the bumped die to the substrate) could not properly image and align the bumped die with the substrate. In addition, it was believed that roughening of the contact surfaces of the bumps may cause problems subsequent to reflow, including void formation and perhaps reliability problems.
Further, it was found that according to the bumped die in which the bumps are laid out in an array fashion at a relatively small pitch (i.e. high density), the carrier contacts 18 had to be placed at an equally fine pitch, separated by even smaller spacing than the C4 bumps, due to the flared xe2x80x9cmushroomxe2x80x9d top of the carrier contacts 18. In this regard, it was found that the side of the die which is formed subsequent to the sawing operation is not generally formed with the precision required for the die to properly align with the carrier contacts. Accordingly, slight shifts in formation of the side surfaces of the die cause shifting of the die, whereby the bumps straddle adjacent carrier contacts which cause undesirable shorting. This phenomena is due to the fact that the sides of the die are used for alignment purposes within the carrier 10.
In an attempt to address the deficiencies of the known carrier, the present inventors considered using more sharply pointed carrier contacts. However, it was determined that such carrier contacts would not be practically feasible for a number of reasons. For example, such contacts would cause problems with the vision equipment for alignment, voids in the bumps, etc.
Other methods for testing bumped die include a technique wherein a temporary solder joint is formed, between the C4 bump and a test substrate, and testing equipment connected to the I/O pins or BGA (ball grid array) balls of the substrate. According to this technique, the bumped die is placed on a substrate having relatively small contact pads, and reflow is carried out. However, this technique requires physical separation of the bumped die from the substrate, after reflow and testing, which is laborious and not cost effective.
Accordingly, it is quite clear that a need exists in the art for testing bumped semiconductor die utilizing a novel known good die carrier particularly adapted for bumped die.